1. Field of the Invention
The invention relates to an unpolished semiconductor wafer and to a method for producing an unpolished semiconductor wafer.
2. Background Art
According to the prior art, semiconductor wafers are produced in a multiplicity of successive process steps, which can generally be subdivided as follows:    a) production of a single crystal of semiconductor material (crystal pulling);    b) separation of the semiconductor single crystal into individual wafers (wafering, sawing);    c) mechanical processing of the semiconductor wafers;    d) chemical processing of the semiconductor wafers;    e) chemical-mechanical processing of the semiconductor wafers.Added to this, there are a multiplicity of substeps such as cleaning, measuring and packaging.
A single crystal is conventionally produced by pulling a semiconductor single crystal from a melt (CZ or Czochralski method) or by recrystallizing a rod of polycrystalline semiconductor material (FZ or floating zone method).
Wire sawing (multi-wire slicing, MWS) and internal hole sawing are known as separating methods. In wire sawing, a multiplicity of semiconductor wafers are separated from a crystal piece in one working step. Wire saws have a wire web which is formed by the saw wire wound around two or more wire guide rolls. The saw wire may be coated with cutting grain (diamond wire MWS). When using wire saws with a saw wire without firmly bound cutting grain, cutting grain is supplied in the form of a suspension during the separation process (slurry MWS). The wire web, in which the saw wire is arranged in the form of wire sections lying parallel next to one another, penetrates through the crystal piece during the separation process. The penetration of the wire web is caused by a forward movement device, which guides the crystal piece against the wire web or the wire web against the crystal piece.
In internal hole sawing, a circularly round rotating saw blade which is clamped on its outer circumference in a clamp system, has a central circular bore (internal hole) whose inner circumferential region is provided with a cutting coat. The crystal piece to be cut is fastened in a frame by means of an adapter device and is brought by an adjustment mechanism into the intended cutting position and held there. The crystal and blade are subjected to relative motion by which the cutting edge works radially through the crystal piece until a semiconductor wafer is finally separated.
Mechanical processing serves to remove saw corrugations, to abrade surface layers which have suffered crystalline damage by the rough sawing processes or have been contaminated by the saw wire, and above all to provide for global planarization of the semiconductor wafers. Here, sequential single-side grinding (SSG) methods and simultaneous double-disk grinding (DDG) methods as well as lapping are used.
In single-side grinding, the semiconductor wafer is held on the rear by a support (chuck) and planarized on the front side by a cup grinding disk or, which is less customary, by an outer grinding disk with rotation of the support and the grinding disk and slow radial adjustment.
In simultaneous double-disk grinding (DDG), the freely suspended semiconductor wafer is simultaneously processed on both sides between two grinding disks mounted on opposite collinear spindles, while being guided substantially free from constraining forces axially between a water cushion (hydrostatic principle) or air cushion (aerostatic principle) acting on the front and rear sides, and loosely prevented from floating radially by means of a surrounding thin guide ring or by individual radial spokes.
Distinction can be made between coarse grinding and fine grinding depending on the granularity and binding of the abrasive grains of the grinding disks. In the scope of this invention, fine grinding means that grinding disks are used with synthetic resin-bonded abrasive with an average grain size of #1500 (mesh) or finer (larger mesh number). When coarse grinding is involved, this means a grinding step using grinding disks with average grain sizes of less than #1500. Such grinding disks are available, for example, from Disco Corp. Japan. The average grain size is specified according to Japanese Industrial Standard JIS R 6001:1998.
In lapping, while supplying a suspension containing abrasives, the semiconductor wafers are moved under pressure between upper and lower working disks, which usually consist of steel and are provided with channels for improved distribution of the lapping agent, semiconductor material thereby being removed. The semiconductor wafers lie in suitably dimensioned recesses of so-called rotor disks, the rotor disks being set in rotation by means of an inner and an outer drive rim and the semiconductor wafers thus being guided on a geometrical path determined by the drive parameters. The pressure is usually transmitted via a pneumatically, hydraulically or electrically operating force transmission device from the upper working disk onto the semiconductor wafers and the lapping agent lying between the working disks and the semiconductor wafers.
The edge of the semiconductor wafer, including any existing mechanical markings such as an orientation notch or an essentially rectilinear flat on the wafer edge, is usually also processed (edge notch grinding). To this end, conventional grinding steps with profiled grinding disks, belt grinding methods with continuous or periodic forward tool movement or integrated edge rounding methods (edge grinding and edge polishing in one step) are used.
The group of chemical processing steps comprises cleaning steps to remove contaminants, and etching steps to remove damaged surface layers and to reduce surface roughness. Etching steps with alkaline media, particularly those based on NaOH (sodium hydroxide), KOH (potassium hydroxide) or TMAH (tetramethylammonium hydroxide) and etching steps with acidic media, in particular based on mixtures of HNO3/HF (nitric acid/hydrofluoric acid) or combinations of such etching steps, are employed for etching. Other etching methods such as plasma etching are occasionally also used.
The group of chemical-mechanical processing steps comprises polishing steps by which, through partial chemical reaction and partial mechanical material abrasion, the surface is smoothed with respect to local planarity, nanotopology and surface roughness, and residual damage of the surface is removed. Polishing generally comprises one or more prepolishing (material removal polishing) and haze-free (fine polishing) polishing steps and optionally also intermediate steps (buff polishing).
DE 10215960 A1 describes a method for producing semiconductor wafers, in which the following process sequence is employed:
a) separating a semiconductor single crystal into wafers,
b) lapping the front and rear sides of the semiconductor wafers,
c) etching the front and rear sides of the semiconductor wafers,
d) fine grinding at least the front sides of the semiconductor wafers,
e) etching the front and rear sides of the semiconductor wafers,
f) polishing the semiconductor wafers.
During the production of semiconductor wafers for CMOS (Complementary Metal Oxide Semiconductor) applications, fine polishing of at least the front side of the semiconductor wafer as per step f) in DE 10215960 is provided by all known methods, in order to meet the stringent requirements for global and local planarity and nanotopology of starting materials for the production of these components. For the production of semiconductor wafers for applications in power electronics or for the fabrication of discrete components, however, these methods are too elaborate and uneconomical. Semiconductor wafers intended for such applications are therefore usually unpolished wafers which are lapped and treated with an etchant after separation from a single crystal. Polishing of the semiconductor wafers is not provided in this case. Attempts are made to achieve the planarity and gloss requirements of the semiconductor wafer merely by lapping and etching.
A method with a sawing-lapping-etching process sequence is also known, for example, from U.S. Pat. No. 6,063,301. A disadvantage of this method is that lapping leads to damage deep into the interior of the crystal lattice, which usually necessitates increased material removal during the subsequent etching in order to remove this damage. A high etch removal leads to a deterioration of the planarity of the semiconductor wafer.
A sawing-etching-lapping-etching sequence is described in U.S. Pat. No. 5,899,744. The material removal during lapping is intended to be reduced by carrying out a first etching treatment of the semiconductor wafer before the lapping step. This method is also disadvantageous, since further deterioration of the planarity of the semiconductor wafer is to be expected from two etching steps. An inferior surface roughness of the semiconductor wafers produced, namely less than 100 nm, is reported in all known methods in which a lapping step is provided.
It is proposed in DE 10237247 A1 to separate the semiconductor wafer from a single crystal, subject the semiconductor wafer to treatment with etchant, and subsequently clean the wafer, no further mechanical processing steps such as grinding, lapping or polishing being provided. A gloss-etched semiconductor wafer with a reflectivity of at least 70% can be produced by this method, the reflectivity is determined by projecting light onto the semiconductor wafer at a selected angle (40 to 80°) and measuring the reflected component. Semiconductor wafers with an unsatisfactory surface roughness of 0.1-0.5 μm are disclosed.
Another disadvantage of the foregoing method is that again, a high etching removal is provided, which entails a deterioration of the planarity or the microstructure of the surface of the wafer. This microstructure is distinguished by visually perceptible roughness variations over length scales of 50-2000 μm and is also known to those skilled in the art as an “orange peel” structure. Such a microstructure leads to a limitation of the possible linewidth in photolithographic processes during the production of components. This linewidth is the minimum distance between two objects of the overall component, for example the distance between the opposing edges of two interconnects.